RISC-V Processor

In a team of two students, I designed a single-cycle processor that implemented a portion of the RISC-V instruction set architecture, as a final project for Brown ENGN 1640 - Design of Computing Systems, taught by Professor Xinming Huang.

Our Verilog design was stable at frequencies slightly above 100 MHz. Full credit on the project was granted for designs that could compute factorials at clock frequencies of at least 80 MHz.

The processor supported the following instructions:

  • ADD, ADDI, and SUB
  • LW and SW
  • AND and OR
  • MUL
  • SLLI
  • BEQ and BNE
  • JAL and JALR